1. Field of the Invention
The present invention relates to a COF (chip-on-film) flexible printed wiring board; e.g., a COF film carrier tape or a COF flexible printed circuit (FPC), for mounting electronic devices such as ICs and LSIs thereon. The invention also relates to a method of producing the COF flexible printed wiring board. The term “COF flexible printed wiring board” refers to a flexible printed wiring board onto which electronic devices (chips) are to be mounted. The term “COF film carrier tape” refers to a film substrate assuming the form of tape onto which electronic devices (chips) are to be mounted.
2. Description of the Related Art
Development of the electronics industry has been accompanied by sharp demand for printed-circuit boards for mounting electronic devices thereon, such as ICs (Integrated Circuits) and LSIs (Large-Scale Integrated circuits). Manufacturers have attempted to realize small-size, lightweight, and high-function electronic equipment, which has long been desired. To this end, manufactures have recently come to employ a film carrier tape, such as a TAB (tape automated bonding) tape, a T-BGA (ball grid array) tape, an ASIC tape, or an FPC (flexible printed circuit). Use of film carrier tapes for mounting electronic devices thereon has become of increasing importance, especially for manufacturers of personal computers, cellular phones, and other electronic equipment employing a liquid crystal display (LCD) that must have high resolution and flatness, as well as a narrow screen-frame area.
In addition, in order to attain higher-density mounting on a narrower space, mounting of bare IC chips directly on a flexible printed wiring board has been employed. Such a product is called COF (chip-on-film).
Since the flexible printed wiring board serving as a substrate of COFs does not have a device hole, a laminate film obtained by laminating in advance a conductor layer and an insulating layer is employed as the flexible printed wiring board. When IC chips are directly mounted on the wiring pattern, positioning is performed on the basis of marks such as an inner lead and a positioning mark which are visible through the insulating layer, followed by joining the IC chips and the wiring pattern; i.e., the inner lead, by means of a heating tool (see, for example, Japanese Patent Application Laid-Open (kokai) No. 2002-289651, FIGS. 4 to 6 and paragraphs [0004] and [0005]).
Such semiconductor chips are mounted while the insulating layer is in direct contact with a heating tool. Since the insulating layer is heated to a considerably high temperature by the heating tool during mounting, a portion of the insulating layer is caused to adhere to the heating tool by melting, thereby causing stoppage of a production apparatus. In addition, unfavorable deformation of the carrier tape occurs. In the case where the insulating layer is melt-adhered to the heating tool, the heating tool is stained, thereby deteriorating reliability and productivity.
Such melt adhesion to the heating tool is critical when semiconductor chips are mounted on a COF film carrier tape or a COF FPC having no device hole.